Robust Sub-Powered Asynchronous Logic

Abstract : While MOSFET technology scaling provides substantial advantages in terms of Integrated Circuits (ICs) speed and energy consumption those are coming at the expense of a higher sensitivity to process, voltage, and temperature (PVT) variations. To alleviate this lack of robustness, which became a critical issue in advanced deep sub-micron technologies, many mechanisms have been proposed at all abstraction levels from device and circuit up to architecture and application software. Among those, a natural solution is to rely on asynchronous logic design style as by its nature is less sensitive to delay variations, which are the "de facto" PVT variations consequence. Several asynchronous logic families have been introduced as follows: (i) Single-rail energy effective logic but still time-sensitive as it relies on delay elements and (ii) Dual-rail robust but more power hungry logic. In this paper we introduce a robust asynchronous logic family which does not rely on timing assumptions and/or delay elements and can operate with sub-powered devices. The key element behind our proposal is a simplified completion detection mechanism which makes it substantially more energy effective when compared with other dual-rail approaches. A 32-bit Ripple Carry Adder (RCA) is implemented in 65nm and 45nm CMOS process to evaluate the practicability of our approach. Firstly, the Optimal Energy Point (OEP) of the proposed RCA is investigated by scaling VDD from 0.4V to 0.2V (50mV interval), where the OEP occurs at 0.25V for both technologies. Secondly, while comparing the energy consumption with the corresponding single-rail benchmark at its OEP in 65nm process, 30% (34 fJ for 65nm) and 40% (54fJ for 45nm after scaling) energy savings are achieved respectively. More impressive (10x better) energy efficiency and reasonable performance are obtained over dual-rail counterparts. At last, process variations concerned Monte Carlo simulation is executed to demonstrate the robustness of our methodology as well to explore the response of OEP, which remains unchanged at 0.25V.
Type de document :
Communication dans un congrès
PATMOS - International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep 2014, Palma de Mallorca, Spain. IEEE, 2014, 〈http://www.patmos-conf.org/〉. 〈10.1109/PATMOS.2014.6951863〉
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https://hal.inria.fr/hal-01063821
Contributeur : Arnaud Tisserand <>
Soumis le : samedi 13 septembre 2014 - 16:31:40
Dernière modification le : mardi 16 janvier 2018 - 15:54:13

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Jiaoyan Chen, Arnaud Tisserand, Emanuel Popovici, S. D. Cotofana. Robust Sub-Powered Asynchronous Logic. PATMOS - International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep 2014, Palma de Mallorca, Spain. IEEE, 2014, 〈http://www.patmos-conf.org/〉. 〈10.1109/PATMOS.2014.6951863〉. 〈hal-01063821〉

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