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Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip

Abstract : A fault-tolerant routing algorithm in Network-on-Chip architectures provides adaptivity for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problems if improperly implemented. Formal verification techniques are needed to check the correctness of the design. This paper performs formal analysis on an extension of the link-fault tolerant Network-on-Chip architecture introduced by Wu et al. that supports multiflit wormhole routing. This paper describes several lessons learned during the process of constructing a formal model of this routing architecture. Finally, this paper presents how the deadlock freedom and tolerance to a single-link fault is verified for a two-by-two mesh version of this routing architecture.
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Contributor : Wendelin Serwe Connect in order to contact the contributor
Submitted on : Wednesday, September 17, 2014 - 11:39:21 AM
Last modification on : Wednesday, February 2, 2022 - 3:57:07 PM
Long-term archiving on: : Thursday, December 18, 2014 - 10:47:02 AM



Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro yoneda, Hao Zheng, et al.. Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. 19th International Conference on Formal Methods for Industrial Critical Systems, FMICS 2014, Sep 2014, Florence, Italy. pp.48-62, ⟨10.1007/978-3-319-10702-8_4⟩. ⟨hal-01064829⟩



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