Hardware/Software Helper Thread Prefetching On Heterogeneous Many Cores

Bharath Narasimha Swamy 1 Alain Ketterlin 2, 3, 4 André Seznec 1
1 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
4 CAMUS - Compilation pour les Architectures MUlti-coeurS
Inria Nancy - Grand Est, ICube - Laboratoire des sciences de l'ingénieur, de l'informatique et de l'imagerie
Abstract : —Heterogeneous Many Cores (HMC) architectures that mix many simple/small cores with a few complex/large cores are emerging as a design alternative that can provide both fast sequential performance for single threaded workloads and power-efficient execution for through-put oriented parallel workloads. The availability of many small cores in a HMC presents an opportunity to utilize them as low-power helper cores to accelerate memory-intensive sequential programs mapped to a large core. However, the latency overhead of accessing small cores in a loosely coupled system limits their utility as helper cores. Also, it is not clear if small cores can execute helper threads sufficiently in advance to benefit applications running on a larger, much powerful, core. In this paper, we present a hardware/software framework called core-tethering to support efficient helper threading on heterogeneous many-cores. Core-tethering provides a co-processor like interface to the small cores that (a) enables a large core to directly initiate and control helper execution on the helper core and (b) allows efficient transfer of execution context between the cores, thereby reducing the performance overhead of accessing small cores for helper execution. Our evaluation on a set of memory intensive programs chosen from the standard benchmark suites show that, helper threads using moderately sized small cores can significantly accelerate a larger core compared to using a hardware prefetcher alone. We find that a small core provides a good trade-off against using an equivalent large core to run helper threads in a HMC. Additionally, helper prefetching on small cores when used along with hardware prefetching, can provide an alternate design point to growing instruction window size for achieving higher sequential performance on memory intensive applications.
Type de document :
Communication dans un congrès
2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Oct 2014, Paris, France. 〈10.1109/SBAC-PAD.2014.39〉
Liste complète des métadonnées

https://hal.inria.fr/hal-01087752
Contributeur : Narasimha Swamy Bharath <>
Soumis le : mercredi 26 novembre 2014 - 15:43:49
Dernière modification le : mercredi 16 mai 2018 - 11:23:28

Identifiants

Citation

Bharath Narasimha Swamy, Alain Ketterlin, André Seznec. Hardware/Software Helper Thread Prefetching On Heterogeneous Many Cores. 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Oct 2014, Paris, France. 〈10.1109/SBAC-PAD.2014.39〉. 〈hal-01087752〉

Partager

Métriques

Consultations de la notice

380