Design Flow and Run-Time Management for Compressed FPGA Configurations

Abstract : The aim of partially and dynamically reconfigurable hardware is to provide an increased flexibility through the load of multiple applications on the same reconfigurable fabric at the same time. However, a configuration bit-stream loaded at runtime should be created offline for each task of the application. Moreover, modern applications use a lot of specialized hardware blocks to perform complex operations, which tends to cancel the "single bit-stream for a single application" paradigm, as the logic content for different locations of the reconfigurable fabric may be different. In this paper we propose a design flow for generating compressed configuration bit-streams abstracted from their final position on the logic fabric. Those configurations will then be decoded and finalized in real-time and at run-time by a dedicated reconfiguration controller to be placed at a given physical location. Our experiments show that densely routed applications gain the most with a compression factor of more than 2× using the finest cluster size, but coarser coding can be implemented to achieve a compression factor up to 10×.
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Communication dans un congrès
DATE - Design, Automation and Test in Europe, Mar 2015, Grenoble, France. 2015, 〈http://www.date-conference.com/date15/〉
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  • HAL Id : hal-01089319, version 1

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Christophe Huriaux, Antoine Courtay, Olivier Sentieys. Design Flow and Run-Time Management for Compressed FPGA Configurations. DATE - Design, Automation and Test in Europe, Mar 2015, Grenoble, France. 2015, 〈http://www.date-conference.com/date15/〉. 〈hal-01089319〉

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