Fast and Secure Finite Field Multipliers

Danuta Pamula 1, 2 Arnaud Tisserand 2, *
* Auteur correspondant
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : The paper presents details on fast and secure GF (2^m) multipliers dedicated to elliptic curve cryptography applications. Presented design approach aims at high efficiency and security against side channel attacks of a hardware multi-plier. The security concern in the design process of a GF (2^m) multiplier is quite a novel concept. Basing on the results obtained in course of conducted research it is argued that, as well as efficiency of the multiplier impacts the efficiency of the cryptoprocessor, the security level of the multiplier impacts the security level of the whole cryptoprocessor. Thus the goal is to find a tradeoff, to compromise efficiency, in terms of speed and area, and security of the multiplier. We intend to secure the multiplier by masking the operation, either by uniformization or by randomization of the power consumption of the device during its work. The design methodology is half automated. The analyzed field sizes are the standard ones, which ensure that a cryptographic system is mathematically safe. The described architecture is based on principles of Mastrovito multiplication method. It is very flexible and enables to improve the resistance against side channel attacks without degrading the multiplier efficiency.
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Danuta Pamula, Arnaud Tisserand. Fast and Secure Finite Field Multipliers. DSD: Euromicro Conference on Digital System Design, Aug 2015, Funchal, Portugal. 2015, 〈http://paginas.fe.up.pt/~dsd-seaa-2015/dsd2015/〉. 〈10.1109/DSD.2015.46〉. 〈hal-01169851〉

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