Sequential and Parallel Code Sections are Different: they may require different Processors

Surya Narayanan Natarajan 1 André Seznec 1
1 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Amdhal's law says that, we cannot go faster than the serial 1 section of the program though we might have infinite processing resource. Therefore, to obtain optimal performance in many-core era, we should exploit both Thread Level Parallelism (TLP) and Instruction Level Parallelism (ILP) : TLP by extracting more parallelism and ILP by making sequential cores faster. An application parallelized using shared memory model application can be divided into: 1. Serial section that runs only in one core and 2. Parallel sections that run simultaneously in multiple cores. In this paper, we characterize the inherent program behavior of the serial and parallel sections to find the difference between them in currently available multi-threaded applications. Our analysis shows that, the micro-architectural resource requirements of both these sections are different, thereby affirming that heterogeneous cores with few complex cores and many small cores will benefit most applications in many-core era.
Type de document :
Communication dans un congrès
PARMA-DITAM '15 - 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures, Jan 2015, Amsterdam, Netherlands. ACM, pp.13-18, 2015, 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms. 〈10.1145/2701310.2701314〉
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https://hal.inria.fr/hal-01170061
Contributeur : Surya Narayanan Natarajan <>
Soumis le : jeudi 2 juillet 2015 - 15:47:00
Dernière modification le : mercredi 11 avril 2018 - 02:00:39

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Surya Narayanan Natarajan, André Seznec. Sequential and Parallel Code Sections are Different: they may require different Processors. PARMA-DITAM '15 - 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures, Jan 2015, Amsterdam, Netherlands. ACM, pp.13-18, 2015, 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms. 〈10.1145/2701310.2701314〉. 〈hal-01170061〉

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