Skip to Main content Skip to Navigation
Conference papers

Small FPGA based Multiplication-Inversion Unit for Normal Basis Representation in $GF(2^m)$

Jérémy Métairie 1 Arnaud Tisserand 1, * Emmanuel Casseau 1
* Corresponding author
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Halving methods have been proposed for parallel implementation of ECC primitives on multicore processors. In hardware, they can also provide protection against some side channel attacks (thanks to parallel independent operations). But they require affine coordinates for curve points and costly inversions. We propose a new combined multiplication-inversion unit for binary field extensions and halving based ECC methods optimized for FPGAs. We target small area solutions compared to very fast but costly ones from state-of-art. Our solution is based on permuted normal basis, Massey-Omura multiplication and Itoh-Tsujii inversion algorithms. Our FPGA implementations show better efficiency for large fields.
Complete list of metadata

Cited literature [6 references]  Display  Hide  Download
Contributor : Arnaud Tisserand Connect in order to contact the contributor
Submitted on : Thursday, July 16, 2015 - 8:39:32 PM
Last modification on : Tuesday, October 19, 2021 - 11:58:51 PM
Long-term archiving on: : Wednesday, April 26, 2017 - 6:52:52 AM


  • HAL Id : hal-01175712, version 1


Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau. Small FPGA based Multiplication-Inversion Unit for Normal Basis Representation in $GF(2^m)$. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. ⟨hal-01175712⟩



Les métriques sont temporairement indisponibles