Small FPGA based Multiplication-Inversion Unit for Normal Basis Representation in $GF(2^m)$

Jérémy Métairie 1 Arnaud Tisserand 1, * Emmanuel Casseau 1
* Auteur correspondant
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Halving methods have been proposed for parallel implementation of ECC primitives on multicore processors. In hardware, they can also provide protection against some side channel attacks (thanks to parallel independent operations). But they require affine coordinates for curve points and costly inversions. We propose a new combined multiplication-inversion unit for binary field extensions and halving based ECC methods optimized for FPGAs. We target small area solutions compared to very fast but costly ones from state-of-art. Our solution is based on permuted normal basis, Massey-Omura multiplication and Itoh-Tsujii inversion algorithms. Our FPGA implementations show better efficiency for large fields.
Type de document :
Communication dans un congrès
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. 2015, <http://www.isvlsi.org/>
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https://hal.inria.fr/hal-01175712
Contributeur : Arnaud Tisserand <>
Soumis le : jeudi 16 juillet 2015 - 20:39:32
Dernière modification le : mercredi 2 août 2017 - 10:07:08
Document(s) archivé(s) le : mercredi 26 avril 2017 - 06:52:52

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  • HAL Id : hal-01175712, version 1

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Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau. Small FPGA based Multiplication-Inversion Unit for Normal Basis Representation in $GF(2^m)$. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. 2015, <http://www.isvlsi.org/>. <hal-01175712>

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