Cost-Effective Speculative Scheduling in High Performance Processors

Abstract : To maximize performance, out-of-order execution processors sometimes issue instructions without having the guarantee that operands will be available in time; e.g. loads are typically assumed to hit in the L1 cache and dependent instructions are issued assuming a L1 hit. This form of speculation – that we refer to as speculative scheduling – has been used for two decades in real processors, but has received little attention from the research community. In particular, as pipeline depth grows and the distance between the Issue and the Execute stages increases, it becomes critical to issue dependents on variable-latency instructions as soon as possible, rather than to wait for the actual cycle at which the result becomes available. Unfortunately, due to the uncertain nature of speculative scheduling, the scheduler may wrongly issue an instruction that will not have its source(s) on the bypass network when it reaches the Execute stage. Therefore, this instruction must be canceled and replayed, which can potentially impair performance and increase energy consumption. In this work, we do not present a new replay mechanism. Rather, we focus on ways to reduce the number of replays that are agnostic of the replay scheme. First, we propose an easily implementable, low-cost solution to reduce the number of replays caused by L1 bank conflicts. Schedule Shifting always assumes that, given a dual-load issue capacity, the second load issued in a given cycle will be delayed because of a bank conflict. Its dependents are thus always issued with a corresponding delay. Second, we also improve on existing L1 hit/miss prediction schemes by taking into account instruction criticality. That is, for some criterion of criticality and for loads whose hit/miss behavior is hard to predict, we show that it is more cost-effective to stall dependents if the load is not predicted critical. In total, in our experiments assuming a 4-cycle issue-to- execute delay, we found that the vast majority of instructions replays due to L1 data cache banks conflicts – 78.0% – and L1 hit mispredictions – 96.5% – can be avoided, thus leading to a 3.4% performance gain and a 13.4% decrease in the number of issued instructions, over a baseline speculative scheduling scheme.
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Communication dans un congrès
International Symposium on Computer Architecture, Jun 2015, Portland, United States. 42, pp.247-259, Proceedings of the International Symposium on Computer Architecture. 〈http://www.ece.cmu.edu/calcm/isca2015〉. 〈10.1145/2749469.2749470〉
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Arthur Perais, André Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten. Cost-Effective Speculative Scheduling in High Performance Processors. International Symposium on Computer Architecture, Jun 2015, Portland, United States. 42, pp.247-259, Proceedings of the International Symposium on Computer Architecture. 〈http://www.ece.cmu.edu/calcm/isca2015〉. 〈10.1145/2749469.2749470〉. 〈hal-01193233〉

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