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Dense Symmetric Indefinite Factorization on GPU Accelerated Architectures

Marc Baboulin 1, 2 Jack Dongarra 3 Adrien Rémy 1, 2 Stanimire Tomov 3 Ichitaro Yamazaki 3
1 POSTALE - Performance Optimization by Software Transformation and Algorithms & Librairies Enhancement
LRI - Laboratoire de Recherche en Informatique, Inria Saclay - Ile de France
2 LRI - Laboratoire de Recherche en Informatique
3 ICL - Innovative Computing Laboratory [Knoxville]
Abstract : We study the performance of dense symmetric indefinite factorizations (Bunch-Kaufman and Aasen's algorithms) on multicore CPUs with a Graphics Processing Unit (GPU). Though such algorithms are needed in many scientific and engineering simulations, obtaining high performance of the factorization on the GPU is difficult because the pivoting that is required to ensure the numerical stability of the factorization leads to frequent synchronizations and irregular data accesses. As a result, until recently, there has not been any implementation of these algorithms on hybrid CPU/GPU architectures. To improve their performance on the hybrid architecture, we explore different techniques to reduce the expensive communication and synchronization between the CPU and GPU, or on the GPU. We also study the performance of a symmetric indefinite factorization with no pivoting combined with the preprocessing technique based on Random Butterfly Transformations. Though such transformations only have probabilistic results on the numerical stability, they avoid the pivoting and obtain a great performance on the GPU.
Keywords : GPU computation randomization communication-avoiding dense symmetric indefinite factorization
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Conference papers
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https://hal.inria.fr/hal-01223022
Contributor : Marc Baboulin <>
Submitted on : Sunday, November 1, 2015 - 3:15:24 PM
Last modification on : Thursday, July 8, 2021 - 3:47:03 AM

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CNRS | INRIA | UMR8623 | LRI-PARSYS | CENTRALESUPELEC | GS-COMPUTER-SCIENCE

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Marc Baboulin, Jack Dongarra, Adrien Rémy, Stanimire Tomov, Ichitaro Yamazaki. Dense Symmetric Indefinite Factorization on GPU Accelerated Architectures. International Conference on Parallel Processing and Applied Mathematics, Sep 2015, Krakow, Poland. pp.86-95, ⟨10.1007/978-3-319-32149-3_9⟩. ⟨hal-01223022⟩

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