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Combining execution pipelines to improve parallel implementation of HMMER on FPGA

Naeem Abbas 1 Steven Derrien 1 Sanjay Rajopadhye 2 Patrice Quinton 1 Alexandre Cornu 3 Dominique Lavenier 3 
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
3 GenScale - Scalable, Optimized and Parallel Algorithms for Genomics
Inria Rennes – Bretagne Atlantique , IRISA-D7 - GESTION DES DONNÉES ET DE LA CONNAISSANCE
Abstract : HMMER is a widely used tool in bioinformatic, based on the Profile Hidden Markov Models. The computation kernels of HMMER, namely MSV and P7Viterbi are very compute intensive, and their data dependencies if interpreted naively, lead to a purely sequential execution. In this paper, we propose a original parallelization scheme for HMMER by rewriting the mathematical formulation, to expose hidden potential parallelization opportunities. Our parallelization scheme targets FPGA technology, and our architecture can achieve 10 times speedup compared with the latest HMMER3 SSE version, without compromising on the sensitivity of original algorithm.
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https://hal.inria.fr/hal-01235328
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Submitted on : Thursday, December 10, 2015 - 8:57:51 AM
Last modification on : Friday, November 18, 2022 - 9:27:28 AM

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Naeem Abbas, Steven Derrien, Sanjay Rajopadhye, Patrice Quinton, Alexandre Cornu, et al.. Combining execution pipelines to improve parallel implementation of HMMER on FPGA. Microprocessors and Microsystems: Embedded Hardware Design , 2015, 39, pp.457-470. ⟨10.1016/j.micpro.2015.06.006⟩. ⟨hal-01235328⟩

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