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Conference Papers Year : 2015

Energy Modeling and Optimization for Tiled Nested-Loop Codes

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We develop a methodology for modeling the energy efficiency of tiled nested-loop codes running on a graphics processing unit (GPU) and use it for energy efficiency optimization. % We use the polyhedral model, a We assume that a highly optimized and parametrized version of a tiled nested -- loop code, either written by an expert programmer or automatically produced by a polyhedral compilation tool -- is given to us as an input. We then model the energy consumption as an analytical function of a set of parameters characterizing the software and the GPU hardware. Most previous attempts at GPU energy modeling were based on low-level machine models that were then used to model whole programs through simulations, or were analytical models that required low level details. In contrast, our approach develops analytical models based on (i) machine and architecture parameters, (ii) program size parameters as found in the polyhedral model and (iii) tiling parameters, such as those that are chosen by auto-or manual tuners. Our model therefore allows efficient optimization of the energy efficiency with respect to a set of parameters of interest. We illustrate the framework on three nested-loop codes: Smith-Waterman, and one-dimensional and two-dimensional Jacobi stencils, and analyze the accuracy of the resulting models. We also show that the models can be used for optimal tile-size selection for energy efficiency. With optimal choice of model parameters the RMS error is less than 4%. Two factors allow us to attain this high accuracy. The first is domain-specificity: we focus only on tile-able nested-loop codes. The second is that we decouple the energy model from a model of the execution time, a known hard problem.
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hal-01250602 , version 1 (05-01-2016)



Nirmal Prajapati, Waruna Ranasinghe, Vamsi Krishna Tandrapati, Rumen Andonov, Hristo Djidjev, et al.. Energy Modeling and Optimization for Tiled Nested-Loop Codes . Parallel and Distributed Processing Symposium Workshop (IPDPSW), May 2015, Hyderabad India. pp.888 - 895 ⟨10.1109/IPDPSW.2015.94⟩. ⟨hal-01250602⟩
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