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Component reuse methodology for multi-clock Data-Flow parallel embedded Systems

Abstract : The growing complexity of new chips and the time-to-market constraints require fundamental changes in the way systems are designed. Systems on Chip (SoC) based on reused components have become an absolute necessity to embedded systems companies that want to remain competitive. However, the design of a SoC is extremely complex because it encompasses a range of difficult problems in hardware and software design. This paper focuses on the design of parallel and multi-frequency applications using flexible components. Flexible parallel components are assembled using a scheduling method which combines the synchronous data-flow principle of balance equations and the polyhedral scheduling technique. Our approach allows a flexible component to be modelled and a full system to be assembled and synthesized with automatically generated wrappers. The work presented here is an extension of previous work. We illustrate our method on a simplified WCDMA system. We discuss the relationship of this approach with multi-clock architecture, latency-insensitive design, multidimensional data-flow systems and stream programming
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https://hal.inria.fr/hal-01300088
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  • HAL Id : hal-01300088, version 1

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Anne Marie Chana, Patrice Quinton, Steven Derrien. Component reuse methodology for multi-clock Data-Flow parallel embedded Systems. Revue Africaine de la Recherche en Informatique et Mathématiques Appliquées, INRIA, 2014, 18, pp.67-92. ⟨hal-01300088⟩

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