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Conference Papers Year : 2016

Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs

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Abstract

Energy-efficiency is one of the most challenging design issues in both embedded and high-performance computing domains. The aim is to reduce as much as possible the energy consumption of considered systems while providing them with the best computing performance. Finding an adequate solution to this problem certainly requires a cross-disciplinary approach capable of addressing the energy/performance trade-off at different system design levels. In this paper, we present an empirical impact analysis of the integration of Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) technologies in multicore architectures when applying some existing compiler optimizations. For that purpose, we use three well-established architecture and NVM evaluation tools: NVSim, gem5 and McPAT. Our results show that the integration of STT-MRAM at cache memory levels enables a significant reduction of the energy consumption (up to 24.2 % and 31 % on the considered multicore and monocore platforms respectively) while preserving the performance improvement provided by typical code optimizations. We also identify how the choice of the clock frequency impacts the relative efficiency of the considered memory technologies.
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Dates and versions

hal-01347354 , version 1 (20-07-2016)

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Pierre-Yves Péneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, et al.. Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. pp.162-169, ⟨10.1109/PATMOS.2016.7833682⟩. ⟨hal-01347354⟩

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