This paper deals with design challenges intrinsic in nowadays heterogeneous System on Chip (SoC) embedding multicore processors and reconfigurable fabrics. These new archi-tectures yield to software/hardware execution model supporting dynamicity and parallelism management at the same level which comes with additional complexity in the design flow. This new hardware paradigm opens many opportunities for research since there is a lack of CAD tools to map efficiently applications on such technology taking into consideration different trade-offs between performance, power consumption, Quality of service (QoS), etc. In this paper, we present preliminary results taking as example the H.264/AVC encoder using the Zynq 7000 based platform.