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Mixed-size Concurrency: ARM, POWER, C/C++11, and SC

Abstract : Previous work on the semantics of relaxed shared-memory concur-rency has only considered the case in which each load reads the data of exactly one store. In practice, however, multiprocessors support mixed-size accesses, and these are used by systems software and (to some degree) exposed at the C/C++ language level. A semantic foundation for software, therefore, has to address them. We investigate the mixed-size behaviour of ARMv8 and IBM POWER architectures and implementations: by experiment, by developing semantic models, by testing the correspondence between these, and by discussion with ARM and IBM staff. This turns out to be surprisingly subtle, and on the way we have to revisit the fundamental concepts of coherence and sequential consistency, which change in this setting. In particular, we show that adding a memory barrier between each instruction does not restore sequential consistency. We go on to extend the C/C++11 model to support non-atomic mixed-size memory accesses, and prove the standard compilation scheme from C11 atomics to POWER remains sound. This is a necessary step towards semantics for real-world shared-memory concurrent code, beyond litmus tests.
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Submitted on : Friday, December 9, 2016 - 3:01:42 PM
Last modification on : Tuesday, January 11, 2022 - 11:16:04 AM
Long-term archiving on: : Thursday, March 23, 2017 - 10:25:11 AM


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  • HAL Id : hal-01413221, version 1



Shaked Flur, Susmit Sarkar, Christopher Pulte, Kyndylan Nienhuis, Luc Maranget, et al.. Mixed-size Concurrency: ARM, POWER, C/C++11, and SC. 44th ACM SIGPLAN Symposium on Principles of Programming Languages (POPL 2017), ACM, Jan 2017, Paris, France. ⟨hal-01413221⟩



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