Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window

Abstract : Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling V dd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However, overclocking, and error detection and correction capabilities of the double sampling methods are limited due to the fixed speculation window which lacks adaptability for tracking variations such as temperature. In this paper, we introduce a dynamic speculation window to be used in double sampling schemes for timing error detection and correction in pipelined logic paths. The proposed method employs online slack measurement and conventional shadow flipflop approach to adaptively overclock or underclock the design and also to detect and correct timing errors due to temperature and other variability effects. We demonstrate this method in the Xilinx Virtex VC707 FPGA for various benchmarks. We achieve a maximum of 71% overclocking with a limited area overhead of 1.9% LUTs and 1.7% flip-flops.
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Communication dans un congrès
ISVLSI, Jul 2016, Pittsburgh, United States. pp.325 - 330, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 〈10.1109/ISVLSI.2016.13〉
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https://hal.inria.fr/hal-01416945
Contributeur : Cédric Killian <>
Soumis le : jeudi 15 décembre 2016 - 10:12:24
Dernière modification le : mercredi 16 mai 2018 - 11:23:27
Document(s) archivé(s) le : jeudi 16 mars 2017 - 17:10:13

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Rengarajan Ragavan, Cedric Killian, Olivier Sentieys. Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window. ISVLSI, Jul 2016, Pittsburgh, United States. pp.325 - 330, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 〈10.1109/ISVLSI.2016.13〉. 〈hal-01416945〉

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