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Flexible Runtime Verification Based On Logical Clock Constraints

Daian Yue 1, 2 Vania Joloboff 1 Frédéric Mallet 3, 4
1 TEA - Tim, Events and Architectures
Inria Rennes – Bretagne Atlantique , IRISA-D4 - LANGAGE ET GÉNIE LOGICIEL
3 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués, Inria de Paris
Abstract : We present in this paper a method and tool for the verification of causal and temporal properties of embedded systems, by analyzing the trace streams resulting from virtual prototypes that combines simulated hardware and embedded software. The proposed method makes it possible to analyze different kinds of properties without rebuilding the simulation models. Logical clocks are used to identify relevant points to put observation probes and thus also reducing the trace streams size. We propose a property specification language, called PSML, and based on behavioral patterns that does not require knowledge of temporal logics. From a given PSML specification, simulation is instrumented to generate a trace and the code is dynamically loaded by the simulator. The resulting trace stream is analyzed by parallel automata generated from the specification. The experiments, developed over the SimSoC virtual prototyping framework, show flexibility, possibility of using multi-core platforms to parallelize simulation and verification, providing fast results.
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Submitted on : Friday, December 23, 2016 - 10:28:22 AM
Last modification on : Friday, January 21, 2022 - 3:16:33 AM
Long-term archiving on: : Tuesday, March 21, 2017 - 10:50:22 AM


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  • HAL Id : hal-01421890, version 1


Daian Yue, Vania Joloboff, Frédéric Mallet. Flexible Runtime Verification Based On Logical Clock Constraints. FDL 2016 - Forum on specification & Design Languages, ECSI, Sep 2016, Bremen, Germany. ⟨hal-01421890⟩



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