Abstract : The operation of a novel unified memory device using two floating-gates is described through experimental characterization of a fabricated proof-of-concept device and confirmed through simulation. The dynamic, nonvolatile, and concurrent modes of the device are described in detail. Simulations show that the device compares favorably to conventional memory devices. Applications enabled by this unified memory device are discussed, highlighting the dramatic impact this device could have on next generation memory architectures.
Andreas Burg; Ayse Coskun; Matthew Guthaus; Srinivas Katkoori; Ricardo Reis. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. Springer, IFIP Advances in Information and Communication Technology, AICT-418, pp.217-233, 2013, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. 〈10.1007/978-3-642-45073-0_12〉
https://hal.inria.fr/hal-01456958
Contributeur : Hal Ifip
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Soumis le : lundi 6 février 2017 - 10:33:17
Dernière modification le : vendredi 1 décembre 2017 - 01:16:00
Document(s) archivé(s) le : dimanche 7 mai 2017 - 12:52:32
Neil Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul Franzon. Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates. Andreas Burg; Ayse Coskun; Matthew Guthaus; Srinivas Katkoori; Ricardo Reis. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. Springer, IFIP Advances in Information and Communication Technology, AICT-418, pp.217-233, 2013, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. 〈10.1007/978-3-642-45073-0_12〉. 〈hal-01456958〉
