Model Checking Memory-Related Properties of Hardware/Software Co-designs

Abstract : Memory safety plays a crucial role in concurrent hardware/software systems and must be guaranteed under all circumstances. Although there exist some approaches for complete verification that can cope with both hardware and software and their interplay, none of them supports pointers or memory. To overcome this problem, we present a novel approach for model checking memory-related properties of digital HW/SW systems designed in SystemC/TLM. The main idea is to formalize a clean subset of the SystemC memory model using Uppaal timed automata. Then, we embed this formal memory model into our previously proposed automatic transformation from SystemC/TLM to Uppaal timed automata. With that, we can fully automatically verify memory-related properties of a wide range of practical applications. We show the applicability of our approach by verifying memory safety of an industrial design that makes ample use of pointers and call-by-reference.
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Communication dans un congrès
Gunar Schirner; Marcelo Götz; Achim Rettberg; Mauro C. Zanella; Franz J. Rammig. 4th International Embedded Systems Symposium (IESS), Jun 2013, Paderborn, Germany. Springer, IFIP Advances in Information and Communication Technology, AICT-403, pp.92-103, 2013, Embedded Systems: Design, Analysis and Verification. 〈10.1007/978-3-642-38853-8_9〉
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Marcel Pockrandt, Paula Herber, Verena Klös, Sabine Glesner. Model Checking Memory-Related Properties of Hardware/Software Co-designs. Gunar Schirner; Marcelo Götz; Achim Rettberg; Mauro C. Zanella; Franz J. Rammig. 4th International Embedded Systems Symposium (IESS), Jun 2013, Paderborn, Germany. Springer, IFIP Advances in Information and Communication Technology, AICT-403, pp.92-103, 2013, Embedded Systems: Design, Analysis and Verification. 〈10.1007/978-3-642-38853-8_9〉. 〈hal-01466696〉

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