Subspace-Based Face Recognition on an FPGA

Abstract : We present a custom hardware system for image recognition, featuring a dimensionality reduction network and a classification stage. We use Bi-Directional PCA and Linear Discriminant Analysis for feature extraction, and classify based on Manhattan distances. Our FPGA-based implementation runs at 75MHz, consumes 157.24mW of power, and can classify a 61 ×49-pixel image in 143.7μs, with a sustained throughput of more than 7,000 classifications per second. Compared to a software implementation on a workstation, our solution achieves the same classification performance (93.3% hit rate), with more than twice the throughput and more than an order of magnitud less power.
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Lazaros Iliadis; Chrisina Jayne. 12th Engineering Applications of Neural Networks (EANN 2011) and 7th Artificial Intelligence Applications and Innovations (AIAI), Sep 2011, Corfu, Greece. Springer, IFIP Advances in Information and Communication Technology, AICT-363 (Part I), pp.84-89, 2011, Engineering Applications of Neural Networks. 〈10.1007/978-3-642-23957-1_10〉
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Pablo Pizarro, Miguel Figueroa. Subspace-Based Face Recognition on an FPGA. Lazaros Iliadis; Chrisina Jayne. 12th Engineering Applications of Neural Networks (EANN 2011) and 7th Artificial Intelligence Applications and Innovations (AIAI), Sep 2011, Corfu, Greece. Springer, IFIP Advances in Information and Communication Technology, AICT-363 (Part I), pp.84-89, 2011, Engineering Applications of Neural Networks. 〈10.1007/978-3-642-23957-1_10〉. 〈hal-01571359〉

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