Skip to Main content Skip to Navigation
Conference papers

Subspace-Based Face Recognition on an FPGA

Abstract : We present a custom hardware system for image recognition, featuring a dimensionality reduction network and a classification stage. We use Bi-Directional PCA and Linear Discriminant Analysis for feature extraction, and classify based on Manhattan distances. Our FPGA-based implementation runs at 75MHz, consumes 157.24mW of power, and can classify a 61 ×49-pixel image in 143.7μs, with a sustained throughput of more than 7,000 classifications per second. Compared to a software implementation on a workstation, our solution achieves the same classification performance (93.3% hit rate), with more than twice the throughput and more than an order of magnitud less power.
Document type :
Conference papers
Complete list of metadata

Cited literature [5 references]  Display  Hide  Download

https://hal.inria.fr/hal-01571359
Contributor : Hal Ifip <>
Submitted on : Wednesday, August 2, 2017 - 11:41:48 AM
Last modification on : Thursday, March 5, 2020 - 5:42:32 PM

File

978-3-642-23957-1_10_Chapter.p...
Files produced by the author(s)

Licence


Distributed under a Creative Commons Attribution 4.0 International License

Identifiers

Citation

Pablo Pizarro, Miguel Figueroa. Subspace-Based Face Recognition on an FPGA. 12th Engineering Applications of Neural Networks (EANN 2011) and 7th Artificial Intelligence Applications and Innovations (AIAI), Sep 2011, Corfu, Greece. pp.84-89, ⟨10.1007/978-3-642-23957-1_10⟩. ⟨hal-01571359⟩

Share

Metrics

Record views

108

Files downloads

212