Poster: Fault-Tolerant Multi-Processor Scheduling with Backup Copy Technique

Petr Dobias 1 Emmanuel Casseau 1 Oliver Sinnen 2
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
2 ECE - Department of Electrical and Computer Engineering [Auckland ]
Abstract : Development of a run-time, self-adaptive scheduling algorithm for Multi-Processor System-on-Chip taking into account faults and thereby treating unreliable system components
Keywords : Fault-tolerant design Mapping and scheduling Multi-processor platform
Document type :
Poster communications
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https://hal.inria.fr/hal-01610745
Contributor : Emmanuel Casseau <>
Submitted on : Thursday, October 5, 2017 - 9:28:52 AM
Last modification on : Friday, September 13, 2019 - 9:49:43 AM

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Poster_DASIP_2017_09_14.pdf
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  • HAL Id : hal-01610745, version 1

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CNRS | UNIV-RENNES1 | IRISA | INRIA | UR1-UFR-ISTIC | UNIV-RENNES

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Petr Dobias, Emmanuel Casseau, Oliver Sinnen. Poster: Fault-Tolerant Multi-Processor Scheduling with Backup Copy Technique. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sep 2017, Dresden, Germany. ⟨hal-01610745⟩

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