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Evaluation of NoC on Multi-FPGA Interconnection Using GTX Transceiver

Abstract : Multi-FPGA platforms are very popular today for pre-silicon verification of complex designs due to their low cost and high speed. The idea is to divide these systems into smaller subsystems and implement each one on a separate chip. The challenge is that the number of IOs available on FPGA remains constant despite the technological evolution. This problem is resolved by multiplexing several cut-signals using the time division multiplexing scheduling mechanism. This structure has a strong effect on the speed of transmission between FPGAs. However, an inter-FPGA bottleneck appears. In this paper, we focus on evaluating the Network-on-Chip on multi-FPGA using the high speed serial transceiver GTX block. In order to speed up the transmission between FPGAs, GTX Transceiver is used to provide a high bandwidth while using fewer pins compared to existing approaches based on ordinary FPGA IOs pins. Depending on the available multi-gigabit transceiver, the bandwidth per connection is between 3.125 and 28 Gb/s which allows for large amounts of data to be moved quickly between multiple FPGAs. In our evaluation, a VC707 platform based on the Virtex-7 device is used. The simulation results show that the proposed architecture provides low area consumption and latencies under different traffic patterns.
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https://hal.inria.fr/hal-01633785
Contributor : Olivier Sentieys <>
Submitted on : Monday, November 13, 2017 - 1:35:32 PM
Last modification on : Saturday, July 11, 2020 - 3:15:31 AM
Long-term archiving on: : Wednesday, February 14, 2018 - 1:19:55 PM

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  • HAL Id : hal-01633785, version 1

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Atef Dorai, Olivier Sentieys, Héléne Dubois. Evaluation of NoC on Multi-FPGA Interconnection Using GTX Transceiver. 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2017, Batumi, Georgia. ⟨hal-01633785⟩

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