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SMURF: Scalar Multiple-precision Unum Risc-V Floating-point Accelerator for Scientific Computing
Abstract : This paper proposes an innovative Floating Point (FP) architecture for Variable Precision (VP) computation suitable for high precision FP computing, based on a refined version of the UNUM type I format. This architecture supports VP FP intervals where each interval endpoint can have up to 512 bits of mantissa. The proposed hardware architecture is pipelined and has an internal word-size of 64 bits. Computations on longer mantissas are performed iteratively on the existing hardware. The prototype is integrated in a RISC-V environment, it is exposed to the user through an instruction set extension. The paper we provide an example of software usage. The system has been prototyped on a FPGA (Field-Programmable Gate Array) platform and also synthesized for a 28nm FDSOI process technology. The respective working frequency of FPGA and ASIC implementations are 50MHz and 600MHz. The estimated chip area is 1.5mm 2 and the estimated power consumption is 95mW. The flops performance of this architecture remains within the range of a regular fixed-precision IEEE FPU while enabling arbitrary precision computation at reasonable cost.
Cited literature [15 references]
https://hal.inria.fr/hal-02087098
Contributor : Florent de Dinechin Connect in order to contact the contributor
Submitted on : Monday, April 1, 2019 - 5:44:32 PM
Last modification on : Tuesday, July 6, 2021 - 2:51:05 PM
Long-term archiving on: : Tuesday, July 2, 2019 - 6:00:30 PM
Contributor : Florent de Dinechin Connect in order to contact the contributor
Submitted on : Monday, April 1, 2019 - 5:44:32 PM
Last modification on : Tuesday, July 6, 2021 - 2:51:05 PM
Long-term archiving on: : Tuesday, July 2, 2019 - 6:00:30 PM
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2019-CoNGA-SMURF.pdf
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