Variable Precision Floating-Point RISC-V Coprocessor Evaluation using Lightweight Software and Compiler Support - Archive ouverte HAL Access content directly
Conference Papers Year :

Variable Precision Floating-Point RISC-V Coprocessor Evaluation using Lightweight Software and Compiler Support

(1) , (1) , (1) , (1) , (2) , (3)
1
2
3

Abstract

The popularity and community-driven development model of RISCV have opened many areas of investigation to researchers and engineers. To overcome some of the IEEE 754 standard’s limitations, one currently emerging avenue for computer architecture and systems research is the area of alternative floating-point computation. The UNUM format, for instance, offers variable precision and much flexibility useful to scientific computing or computational geometry. Programmers usually rely on arbitrary precision libraries such as MPFR (itself depending on GMP). However, there is currently no specialized RISC-V support for these libraries, and little support for variable precision arithmetic across the tool chain in general. We propose a framework to explore the potential of variable precision arithmetic in scientific computing applications on RISC-V processors. This work comprises: (i) a floating-point RISC-V coprocessor which improve accuracy using the UNUM format; (ii) an ISA extension of the RISC-V ISA for the unit, (iii) a programming model for this extension, and (iv) RISC-V optimized routines for the GMP library. Comparing our solution with MPFR on linear systems solvers, we are able to achieve speedups of up to 18× while keeping computational errors within the same order of magnitude. For 512 bits of precision, speedup between 9x and 16x are observed.
Fichier principal
Vignette du fichier
JOST_BOCCO_CARRV2019.pdf (875.4 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

hal-02161621 , version 1 (20-06-2019)

Identifiers

  • HAL Id : hal-02161621 , version 1

Cite

Tiago T Jost, Andrea Bocco, Yves Durand, Christian Fabre, Florent de Dinechin, et al.. Variable Precision Floating-Point RISC-V Coprocessor Evaluation using Lightweight Software and Compiler Support. CARRV 2019 - Third Workshop on Computer Architecture Research with RISC-V, Jun 2019, Phoenix, AZ, United States. pp.1-6. ⟨hal-02161621⟩
356 View
360 Download

Share

Gmail Facebook Twitter LinkedIn More