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The Connection Layout in a Lattice of Four-Terminal Switches

Abstract : A non classical approach to the logic synthesis of Boolean functions based on switching lattices is considered, for which deriving a feasible layout has not been previously studied. All switches controlled by the same literal must be connected together and to an input lead of the chip, and the layout of such connections must be realized in superimposed layers. Inter-layer connections are realized with vias, with the overall goal of minimizing the number of layers needed. The problem shows new interesting combinatorial and algorithmic aspects. Since the specific lattice cell where each switch is placed can be decided with a certain amount of freedom, and one literal among several may be assigned for controlling a switch, we first study a lattice rearrangement (Problem 1) and a literal assignment (Problem 2), to place in adjacent cells as many switches controlled by the same literal as possible. Then we study how to build a feasible layout of connections onto different layers using a minimum number of such layers (Problem 3). We prove that Problem 2 is NP-hard, and Problems 1 and 3 appear also intractable. Therefore we propose heuristic algorithms for the three phases that show an encouraging performance on a set of standard benchmarks.
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https://hal.inria.fr/hal-02321762
Contributor : Hal Ifip <>
Submitted on : Monday, October 21, 2019 - 2:54:56 PM
Last modification on : Monday, October 21, 2019 - 3:12:09 PM
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Anna Bernasconi, Antonio Boffa, Fabrizio Luccio, Linda Pagli. The Connection Layout in a Lattice of Four-Terminal Switches. 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.32-52, ⟨10.1007/978-3-030-23425-6_3⟩. ⟨hal-02321762⟩

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