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Hardware Realization of Krawtchouk Transform using VDHL Modeling and FPGAs

Abstract : In this paper, the authors present a hardware realization of a simplified Krawtchouk transform. The transform is realized on a Xilinx field-programmable gate arrays chip. The hardware is stand-alone and operates on a real-time basis. Very high speed integrated circuit hardware descriptive language structural, behavioral, and data flow modeling are implemented to describe, simulate, and realize the transform. The hardware consists mainly of an 8 /spl times/ 8-2's-complement multiplier, a 16-b accumulator, a 16 /spl times/ 16-b RAM, a 64 /spl times/ 8-b ROM, and a microprogram-based control unit. A brief analysis of the transform and a contrast between its hardware and that of Fourier transform are presented. The hardware is tested by inputting an eight-point data vector to the input pins of the chip. The results of the transform are read from the output pins of the chip. The results are compared with those obtained from a software program executing the same transform for the same input data vector as the hardware. It is found that results from the hardware match those of the software.
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https://hal.inria.fr/inria-00000271
Contributor : Agnès Vidard <>
Submitted on : Wednesday, September 21, 2005 - 4:37:30 PM
Last modification on : Tuesday, April 24, 2018 - 1:54:31 PM

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  • HAL Id : inria-00000271, version 1

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Nazeih Botros, Yang Jian, Philip Feinsilver, René Schott. Hardware Realization of Krawtchouk Transform using VDHL Modeling and FPGAs. IEEE Transactions on Industrial Electronics, Institute of Electrical and Electronics Engineers, 2002, 49 (6), pp.1306-1312. ⟨inria-00000271⟩

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