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Energy-Delay Tradeoff Analysis of ILP-based Compilation Techniques on a VLIW Architecture

Gilles Pokam 1 François Bodin 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : Energy consumption is becoming an important issue on modern processors, especially on embedded systems. While many architectural solutions to reduce energy consumption exist, software solutions on the other hand mostly rely on performance optimization techniques. The rationale behind this latter approach follows the rule that energy consumption is roughly proportional to the execution time. While some ILP techniques allow to increase performance by eliminating redundant instructions, others however do increase the total instruction count, mitigating their benefit as far as energy consumption is concerned. This paper explores the energy-delay tradeoff of ILP enhancing techniques at the compilation level. The goal is to develop a theoretical understanding of the main energy issues involved by forming ILP blocks. We present an analytical methodology which essentially exploits the variations in program performance to identify conditions leading to energy consumption increase. Our results show that there exists a threshold above which ILP enhancing optimizations may necessarily turn into diminishing energy reduction returns. The proposed tradeoff analysis reveals that this can be mainly attributed to the limited available instruction parallelism of applications which causes wasted computation and, to some extent, machine overhead to start dominating the energy consumption in some scenarios where the ILP is pushed above a given threshold.
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Contributor : Rapport de Recherche Inria <>
Submitted on : Tuesday, May 23, 2006 - 5:57:02 PM
Last modification on : Thursday, January 7, 2021 - 4:29:03 PM
Long-term archiving on: : Sunday, April 4, 2010 - 10:25:07 PM


  • HAL Id : inria-00071558, version 1


Gilles Pokam, François Bodin. Energy-Delay Tradeoff Analysis of ILP-based Compilation Techniques on a VLIW Architecture. [Research Report] RR-5026, INRIA. 2003. ⟨inria-00071558⟩



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