Synthesis of Data-Flow Interfaces for Regular Parallel Programs
Résumé
We present a method for generating an interface between an architecture executing a regular program and a host processor, during an hardware-software co-design process. The interface is generated by static analysis of a single assignment Alfa program and of its scheduling. This method is implement- ed in the MMAlpha design environment, and was experimented on a H261 image coder.
Domaines
Autre [cs.OH]
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