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Contention on 2nd Level Cache May Limit the Effectiveness of Simultaneous Multithreading

Sébastien Hily 1 André Seznec 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : Simultaneous multithreading (SMT) is an interesting way of maximizing performance by enhancing processor utilization. We investigate issues involving the behavior of the memory hierarchy with SMT. First, we show that ignoring L2 cache contention leads to strongly over-estimate the performance one can expect and may lead to incorrect conclusions. We then explore the impact of various memory hierarchy parameters. We show that the number of supported threads has to be set-up according to the cache size, that the L1 caches have to be associative and small blocks have to be used. Then, the hardware constraints put on the design of memory hierarchies should limit the interest of SMT to a few threads.
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Submitted on : Wednesday, May 24, 2006 - 1:12:47 PM
Last modification on : Friday, February 4, 2022 - 3:22:07 AM
Long-term archiving on: : Sunday, April 4, 2010 - 11:50:35 PM


  • HAL Id : inria-00073575, version 1


Sébastien Hily, André Seznec. Contention on 2nd Level Cache May Limit the Effectiveness of Simultaneous Multithreading. [Research Report] RR-3115, INRIA. 1997. ⟨inria-00073575⟩



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