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About Effective Cache Miss Penalty on Out-of-Order Superscalar Processors

André Seznec 1 Fabien Lloansi 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : For many years, the performance of microprocessors has depended on the miss ratio of L1 caches. The whole processor would stall on a cache miss. The contribution of a cache miss to the execution time was exactly the miss penalty. Limiting the miss ratio on L1 caches has been a major issue for the last ten years. Studies showed that, for current cache sizes, 32 or 64 bytes cache blocks was a good tradeoff. Today, technology has changed. Most of the newly announced processors implement a very complex superscalar microarchitecture allowing out-of-order execution. On these processors, instruction execution continues while L1 cache misses are serviced by a pipelined L2 cache. In this paper, we show that, on such superscalar processors, the effective contribution of a cache miss to the execution time is quite distinct of the miss use penalty for the missing data or instruction. We also show that the L2 cache busy time becomes a major bottleneck and that decreasing the demanded throughput on this cache tends to become more important than limiting the L1 miss ratio. This favors the use of short cache block sizes. For current L1 cache sizes and a 16-byte bus, a 16 byte block size is shown to be a good trade-off.
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Submitted on : Wednesday, May 24, 2006 - 2:11:42 PM
Last modification on : Friday, February 4, 2022 - 3:22:16 AM
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  • HAL Id : inria-00073968, version 1


André Seznec, Fabien Lloansi. About Effective Cache Miss Penalty on Out-of-Order Superscalar Processors. [Research Report] RR-2726, INRIA. 1995. ⟨inria-00073968⟩



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