Allocating Registers in Multiple Instruction-Issuing Processors

Abstract : This work addresses the problem of scheduling a basic block of operations on a multiple instruction-issuing processor. We show that integrating register constraints into operation sequencing algorithms is a complex problem in itself. Indeed, while scheduling a forest of unit time operations on a processor with $P$ parallel instruction slots can be solved in polynomial time, the problem becomes NP-hard when $P$ is unbounded but only $R$ registers are available. As a result we have devised a concise integer linear programming formulation of this scheduling problem that accounts for both register and instruction issuing constraints. This allows the use of off-the-shelf routines to find optimum solutions, which can then be compared with the results obtained by polynomial-time heuristics. Two such heuristics are given, and their combined results are shown to be optimal in 99.5% of the cases for trees of height at most 6. A byproduct of these experiments is to show that our integer programming formulation is quite practical as it can find an optimum solution for a tree of height 6 in roughly 0.1 seconds on a sparc workstation.
Type de document :
[Research Report] RR-2628, INRIA. 1995
Liste complète des métadonnées

Littérature citée [2 références]  Voir  Masquer  Télécharger
Contributeur : Rapport de Recherche Inria <>
Soumis le : mercredi 24 mai 2006 - 14:24:23
Dernière modification le : vendredi 16 septembre 2016 - 15:19:38
Document(s) archivé(s) le : jeudi 24 mars 2011 - 14:06:05



  • HAL Id : inria-00074059, version 1



Christine Eisenbeis, Franco Gasperoni, Uwe Schwiegelshohn. Allocating Registers in Multiple Instruction-Issuing Processors. [Research Report] RR-2628, INRIA. 1995. 〈inria-00074059〉



Consultations de la notice


Téléchargements de fichiers