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Optimization of Number of Processors in VLSI Arrays

Yannick Saouter 1
1 API - Parallel VLSI Architectures
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : Since the work of Kung, the systolic architectures have proven their efficiency to deal with many scientific algorithms (LU-decomposition, Gauss-Jordan elimination, ...). Since the early eighties, many works have been made in the area of automatic derivation of systolic architectures. In the general case, there are numerous solutions to the same problem. The final choice of the architecture is often done by comparison of performances. There are several criteria which can be considered: global time of computation, number of processors, latency of the circuit... In this article we are especially interested with the number of processors of the final architecture for which we present a heuristic method.
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Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 3:06:08 PM
Last modification on : Thursday, February 11, 2021 - 2:48:03 PM
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  • HAL Id : inria-00074342, version 1


Yannick Saouter. Optimization of Number of Processors in VLSI Arrays. [Research Report] RR-2333, INRIA. 1994. ⟨inria-00074342⟩



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