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MODEE : smoothing branch and instruction cache miss penalties on deep pipelines

Nathalie Drach 1 André Seznec 1
1 CALCPAR - Calculateurs Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : Pipelining is a major technique used in high performance processors. But a fundamental drawback of pipeling is the lost time due to branch instructions. A new organization for implementing branch instructions is presented : the Multiple Instruction Decode Effective Execution (MIDEE) organization. All the pipeline depths may be addressed using this organization. MIDEE is based on the use of double fetch and decode, early computation of the target address for branch instructions and two instruction queues. The double fetch-decode concerns a pair of instructions stored at consecutive addresses. These instructions are then decoded simultaneously, but no execution hardware is duplicated,only useful instructions are effectively executed. A pair of instruction queues are used between the fetch-decode stages and execution stages, this allows to hide branch penalty and most of the instruction cache misses penalty. Trace driven simulations show that the performance of deep pipeline processor may dramatically be improved when the MIDEE organization is implemented : branch penalty is reduced and pipeline stall delay due to instruction cache misses is also decreased.
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https://hal.inria.fr/inria-00074633
Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 3:57:29 PM
Last modification on : Thursday, February 11, 2021 - 2:48:06 PM
Long-term archiving on: : Monday, April 5, 2010 - 12:12:30 AM

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  • HAL Id : inria-00074633, version 1

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Nathalie Drach, André Seznec. MODEE : smoothing branch and instruction cache miss penalties on deep pipelines. [Research Report] RR-2038, INRIA. 1993. ⟨inria-00074633⟩

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