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Semi-inified caches

Nathalie Drach 1 André Seznec 1
1 CALCPAR - Calculateurs Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : Since the gap between main memory access time and processor cycle time is continuously increasing, processor performance dramatically depends on the behavior of caches and particularly on the behavior of small on-chip caches. In this paper, we present a new organisation for on-chip caches : the semi-unified cache organization. In most microprocessors, two physically split caches are used for respectively storing data and instructions. The purpose of the semi-unified cache organization is to use the data cache (resp. instruction cache) as an on-chip second-level cache for instructions (resp. data). Thus the associativity degree of both on-chip caches is artificially increased and the cache spaces respectively devoted to instructions and data are dynamically adjusted. The off-chip miss ratio of a semi-unified cache built with two direct-mapped caches of size S is equal to the miss ratio of a unified two-way set associative cache of size 2S ; yet, the hit time of this semi-unified cache is equal to the hit time of a direct-mapped cache ; moreover both instructions and data may be accessed in parallel as for the split data/instruction cache organization. Since on-chip miss penalty is lower than off-chip miss penalty, trace driven simulations show that using a direct-mapped semi-unified cache organization leads to higher overall system performance than using usual split instruction/data cache organization.
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https://hal.inria.fr/inria-00074831
Contributor : Rapport de Recherche Inria <>
Submitted on : Wednesday, May 24, 2006 - 4:31:47 PM
Last modification on : Thursday, February 11, 2021 - 2:48:06 PM
Long-term archiving on: : Tuesday, April 12, 2011 - 4:08:01 PM

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  • HAL Id : inria-00074831, version 1

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Nathalie Drach, André Seznec. Semi-inified caches. [Research Report] RR-1841, INRIA. 1993. ⟨inria-00074831⟩

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