Skewed-associative caches

André Seznec 1 François Bodin 1
1 CALCPAR - Calculateurs Parallèles
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes
Abstract : During the past decade, microprocessors potential performance has increased at a tremendous rate using RISC concept, higher and higher clock frequencies and parallel / pipelined instruction issuing. As the gap between the main memory access time and the potential average instruction time is always increasing, it has become very important to improve the behavior of the caches, particularly when no secondary cache is used (i.e. on all low cost microprocessor systems ). In order to improve cache hit ratios, set-associative caches are used in most of the new superscalar microprocessors. In this paper, we present a new organization for a multi-bank cache : the skewed-associative cache. Skewed-associative caches have a better behavior than set-associative caches : typically a two-banks skewed-associative cache has the hardware complexity of a two-way set-associative cache, but exhibits the same hit ratio as a four-way set associative cache of the same size.
Type de document :
[Research Report] RR-1655, INRIA. 1992
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Soumis le : mercredi 24 mai 2006 - 16:50:18
Dernière modification le : mercredi 16 mai 2018 - 11:23:14
Document(s) archivé(s) le : mardi 12 avril 2011 - 20:01:42



  • HAL Id : inria-00074902, version 1


André Seznec, François Bodin. Skewed-associative caches. [Research Report] RR-1655, INRIA. 1992. 〈inria-00074902〉



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