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Rapport Année : 1999

Synchronous FPNNs: neural models that fit reconfigurable hardware

Bernard Girau

Résumé

Neural networks are considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be handled by digital hardware devices. Neural network hardware implementations have to reconcile simple hardware topologies with complex neural architectures. A theoretical and practical framework allows this combination by means of some configurable hardware principles applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme, without having any significant loss of approximation capability. This report follows the overview of FPNAs in report 99.R.019: it focuses on a family of FPNA-based neural networks that are more specially adapted to reconfigurable hardware.
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Dates et versions

inria-00098794 , version 1 (26-09-2006)

Identifiants

  • HAL Id : inria-00098794 , version 1

Citer

Bernard Girau. Synchronous FPNNs: neural models that fit reconfigurable hardware. [Intern report] 99-R-143 || girau99u, 1999, 17 p. ⟨inria-00098794⟩
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