Digital VLSI implementation of a multi-precision neural network classifier

Amine Bermak Dominique Martinez 1
1 CORTEX - Neuromimetic intelligence
INRIA Lorraine, LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
Abstract : In this paper a systolic multi-precision digital VLSI classifier referred to as "SysNeuro" is presented. Unlike the usual VLSI implementation of classifiers, this hardware has been designed to achieve variable precision computations. A hardware reconfiguration is obtained by using switch elements to change the hardware connection between adjacent 4-bit neuron building blocks. With this reconfiguration concept it is possible to either increase the precision by pooling together adjacent cells or to increase the number of neurons for low levels of precision. Moreover, the design is easily programmable and can be configured to any artificial neural network (ANN) topology in order to cover various kinds of application. The chip integrates 16/8/4 neurons with a corresponding precision of 4/8/16-bits. A prototype has been successfully realized using 0.7 um CMOS technology.
Type de document :
Communication dans un congrès
6th International Conference on Neural Information Processing - ICONIP'99, Nov 1999, Perth, Australia, 6 p, 1999
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https://hal.inria.fr/inria-00098829
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Soumis le : mardi 26 septembre 2006 - 08:38:55
Dernière modification le : jeudi 11 janvier 2018 - 06:19:48

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  • HAL Id : inria-00098829, version 1

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Amine Bermak, Dominique Martinez. Digital VLSI implementation of a multi-precision neural network classifier. 6th International Conference on Neural Information Processing - ICONIP'99, Nov 1999, Perth, Australia, 6 p, 1999. 〈inria-00098829〉

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