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Conference papers

Digital hardware implementation of 2D compatible neural networks

Bernard Girau 1
1 CORTEX - Neuromimetic intelligence
INRIA Lorraine, LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
Abstract : The work described in this paper aims at developing neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme, without significant loss of approximation capability. It has been achieved thanks to the definition of a set of neural models called Field Programmable Neural Arrays (FPNA). FPNAs may lead to the definition of neural networks adapted to hardware topological constraints. Different such neural networks may be derived from a given FPNA. They are called Field Programmed Neural Networks (FPNN). They reconcile the high connection density of neural architectures with the need of a limited interconnection scheme in hardware implementations. This paper focuses on the definition and implementation of FPNN parallel computation.
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Submitted on : Tuesday, September 26, 2006 - 8:51:17 AM
Last modification on : Friday, February 4, 2022 - 3:30:45 AM


  • HAL Id : inria-00099136, version 1



Bernard Girau. Digital hardware implementation of 2D compatible neural networks. International Joint Conference on Neural Networks, Jul 2000, none, 6 p. ⟨inria-00099136⟩



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