Parallel FPGA implementation of self-organizing maps

Khaled Ben Khalifa Bernard Girau 1 Frédéric Alexandre 1 Mohamed Hedi Bedoui
1 CORTEX - Neuromimetic intelligence
INRIA Lorraine, LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
Abstract : This paper presents an area-saving parallel implementation of a Self-Organizing Map neural network (SOM) on FPGA. The purpose is to make available a finer grain of parallelism to be used in massively SIMD parallel SOM system architectures. We have handled a serial arithmetics (Most Significant Bit First: MSBF and Least Significant Bit First: LSBF), to process the different mathematical operations. Above all, our work has been oriented in such a way to get a light, easy to wear system for classification of vigilance states in humans from electroencephalographic (EEG) signals. The performances of our implementation in terms of area, speed and especially power consumption are highly satisfactory.
Type de document :
Communication dans un congrès
International Conference on Microelectronics - ICM'04, 2004, Tunis, Tunisia, 4 p, 2004
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Soumis le : mardi 26 septembre 2006 - 10:13:58
Dernière modification le : jeudi 11 janvier 2018 - 06:19:48

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  • HAL Id : inria-00100080, version 1

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Khaled Ben Khalifa, Bernard Girau, Frédéric Alexandre, Mohamed Hedi Bedoui. Parallel FPGA implementation of self-organizing maps. International Conference on Microelectronics - ICM'04, 2004, Tunis, Tunisia, 4 p, 2004. 〈inria-00100080〉

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