Abstract : This paper describes a novel Multi-Chip Module (MCM) digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 $\mu$m technology.
Amine Bermak, Dominique Martinez. A compact Multi-Chip-Module Implementation of a Multi-Precision Neural Network Classifier. IEEE International Symposium on Circuits and Systems - ISCAS'2001, May 2001, Sydney, Australia, pp.249-252. ⟨inria-00108072⟩