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CASH Design Space Exploration

Liqiang He 1 Romain Dolbeau 1 André Seznec 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : As the increasing of issue width has diminishing returns with superscalar processor, thread parallelism with a single chip is becoming a reality. In the past few years, both SMT and CMP approaches were first investigated by academics and are now implemented by the industry. In some sense, SMT and CMP represent two extreme design points. CASH parallel processor (for CMP And SMT Hybird) is a possible intermediate design points for on-chip thread parallelism in terms of design complexity and hardware sharing. It retains resource sharing as SMT when such a sharing can be made non-critical for implementation, but resource splitting as CMP wherever resource sharing leads to a superlinear increase of the implementation hardware complexity. This paper explores the multi-dimensional design space for CASH architecture. It compares the performance of single thread running on CASH, SMT and CMP processors. And then the performances of multi-program workloads and parallel workloads are investigated in these processors. At last, It explores the performance varies on CASH with the changing of cache size, and number of associativity of cache. The experiment results show that the CASH processor has a great potential to improve the performances of single thread workload and most of the multi-program workloads, and at the same time maintains a low implementation complexity than the SMT and CMP.
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Submitted on : Tuesday, November 28, 2006 - 9:41:28 AM
Last modification on : Friday, February 4, 2022 - 3:22:03 AM
Long-term archiving on: : Tuesday, April 6, 2010 - 8:07:40 PM


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  • HAL Id : inria-00116799, version 1


Liqiang He, Romain Dolbeau, André Seznec. CASH Design Space Exploration. [Research Report] PI 1815, 2006, pp.59. ⟨inria-00116799⟩



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