A CMOS Image Sensor with on Chip Image Compression based on Predictive Boundary Adaptation and QTD Algorithm

Shoushun Chen 1 Amine Bermak Yan Wang Dominique Martinez 2
2 CORTEX - Neuromimetic intelligence
INRIA Lorraine, LORIA - Laboratoire Lorrain de Recherche en Informatique et ses Applications
Abstract : This paper presents the architecture, algorithm and VLSI hardware of image acquisition, storage and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with non-destructive storage capability using 8-bit Static-RAM device embedded at the pixel level. An adaptive quantization scheme based on Fast Boundary Adaptation Rule (FBAR) and Differential Pulse Code Modulation (DPCM) procedure followed by an on-line Quadrant Tree Decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including 64x64 pixels, read-out and control circuitry as well as the compression processor was implemented in 0.35um CMOS technology with a silicon area of 3.2x3.0 mm2. Simulation results show compression figures corresponding to 0.6-0.8 Bit-per-Pixel (BPP), while maintaining reasonable PSNR levels.
Type de document :
Communication dans un congrès
the 6th IEEE SENSORS Conference, 2007, Atlanta, United States. 2007
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https://hal.inria.fr/inria-00180188
Contributeur : Dominique Martinez <>
Soumis le : jeudi 18 octobre 2007 - 09:21:36
Dernière modification le : jeudi 11 janvier 2018 - 06:19:48

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  • HAL Id : inria-00180188, version 1

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Shoushun Chen, Amine Bermak, Yan Wang, Dominique Martinez. A CMOS Image Sensor with on Chip Image Compression based on Predictive Boundary Adaptation and QTD Algorithm. the 6th IEEE SENSORS Conference, 2007, Atlanta, United States. 2007. 〈inria-00180188〉

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