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Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures

Abstract : As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify their functional behavior (qualitative properties) and to predict their performance (quantitative properties). This paper presents the work currently done in the Multival project (pôle de compétitivité mondial Minalogic), in which verification and performance evaluation tools developed at INRIA and Saarland University are applied to three industrial architectures designed by Bull, CEA/Leti, and STMicroelectronics.
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https://hal.inria.fr/inria-00199914
Contributor : Hubert Garavel <>
Submitted on : Wednesday, December 19, 2007 - 7:48:37 PM
Last modification on : Thursday, November 19, 2020 - 1:00:27 PM
Long-term archiving on: : Monday, April 12, 2010 - 8:35:19 AM

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  • HAL Id : inria-00199914, version 1

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CNRS | INRIA | CEA | LIG | DRT | LETI | CEA-GRE | UGA

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Nicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, et al.. Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures. Special Session at Design, Automation and Test in Europe DATE'08, Mar 2008, (Munich, German Munich, Germany, March 2008, France. ⟨inria-00199914⟩

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