Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Pierre Michaud 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : On each new technology generation, miniaturization permits putting twice as many computing cores on the same silicon area, potentially doubling the processor performance. However, if sequential execution is not accelerated at the same time, Amdahl's law will eventually limit the actual performance. Hence it will be beneficial to have asymmetric multicores where some cores are specialized for fast sequential execution. This specialization may be achieved by architectural means, but it may also be achieved by specializing transistors, voltage, and clock frequency. In the latter case, one of the main constraints is that the power consumption of fast cores is not increased across technology generations. Yet this implies that the instantaneous heat flux in fast cores be potentially doubled on each new generation. A high instantaneous heat flux can be tolerated by doing periodic activity migration. This requires to double the number of fast cores on each new generation, even though only a single fast core can be used at a given time. To keep the chip temperature below the limit, the migration interval must be divided approximately by four on each new generation. We show with an analytical model that this will eventually decrease the apparent level-2 cache size. We show that this problem can be tackled by preparing a certain number of cores before they become active.
Type de document :
[Research Report] RR-6735, INRIA. 2008, pp.17
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Soumis le : mercredi 26 novembre 2008 - 10:58:46
Dernière modification le : vendredi 16 novembre 2018 - 01:29:50
Document(s) archivé(s) le : lundi 7 juin 2010 - 23:23:56


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  • HAL Id : inria-00341851, version 1


Pierre Michaud. Periodic activity migration for fast sequential execution in future heterogeneous multicore processors. [Research Report] RR-6735, INRIA. 2008, pp.17. 〈inria-00341851〉



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