A NUMA Aware Scheduler for a Parallel Sparse Direct Solver

Mathieu Faverge 1, 2, 3 Xavier Lacoste 3 Pierre Ramet 1, 3
2 RUNTIME - Efficient runtime systems for parallel architectures
Inria Bordeaux - Sud-Ouest, UB - Université de Bordeaux, CNRS - Centre National de la Recherche Scientifique : UMR5800
3 SCALAPPLIX - Algorithms and high performance computing for grand challenge applications
Université Bordeaux Segalen - Bordeaux 2, Université Sciences et Technologies - Bordeaux 1, Inria Bordeaux - Sud-Ouest, École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB), CNRS - Centre National de la Recherche Scientifique : UMR5800
Abstract : Over the past few years, parallel sparse direct solvers made significant progress and are now able to solve efficiently industrial three-dimensional problems with several millions of unknowns. An hybrid MPI-thread implementation of our direct solver PaStiX is already well suited for SMP nodes or new multi-core architectures and drastically reduced the memory overhead and improved scalability. In the context of distributed NUMA architectures, a dynamic scheduler based on a work-stealing algorithm has been developed to fill in communication idle times. On these architectures, it is important to take care of NUMA effects and to preserve memory affinity during the work-stealing. The scheduling of communications also needs to be adapted, especially to ensure the overlap by computations. Experiments on numerical test cases will be presented to prove the efficiency of the approach on NUMA architectures. If memory is not large enough to treat a given problem, disks must be used to store data that cannot fit in memory (out-of-core storage). The idle-times due to disk access have to be managed by our dynamic scheduler to prefetch and save datasets. Thus, we design and study specific scheduling algorithms in this particular context.
Type de document :
Communication dans un congrès
PMAA'08, 2008, Neuchâtel, Switzerland. 2008
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Contributeur : Mathieu Faverge <>
Soumis le : vendredi 5 décembre 2008 - 15:02:50
Dernière modification le : jeudi 11 janvier 2018 - 06:22:12


  • HAL Id : inria-00344709, version 1



Mathieu Faverge, Xavier Lacoste, Pierre Ramet. A NUMA Aware Scheduler for a Parallel Sparse Direct Solver. PMAA'08, 2008, Neuchâtel, Switzerland. 2008. 〈inria-00344709〉



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