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Minimizing cache misses in an event-driven network server: A case study of TUX

Sapan Bhatia 1 Charles Consel 1, 2 Julia L. Lawall 3 
1 PHOENIX - Programming Language Technology For Communication Services
INRIA Futurs, Université Sciences et Technologies - Bordeaux 1, École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)
Abstract : We analyze the performance of CPU-bound network servers and demonstrate experimentally that the degradation in the performance of these servers under high-concurrency workloads is largely due to inefficient use of the hardware caches. We then describe an approach to speeding up event-driven network servers by optimizing their use of the L2 CPU cache in the context of the TUX web server, known for its robustness to heavy load. Our approach is based on a novel cache-aware memory allocator and a specific scheduling strategy that together ensure that the total working data set of the server stays in the L2 cache. Experiments show that under high concurrency, our optimizations improve the throughput of TUX by up to 40% and the number of requests serviced at the time of failure by 21%.
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Submitted on : Thursday, January 15, 2009 - 4:57:51 PM
Last modification on : Friday, August 5, 2022 - 12:31:18 PM
Long-term archiving on: : Friday, October 12, 2012 - 9:40:22 AM


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  • HAL Id : inria-00353573, version 1



Sapan Bhatia, Charles Consel, Julia L. Lawall. Minimizing cache misses in an event-driven network server: A case study of TUX. 31st IEEE International Conference on Local Computer Networks, Nov 2006, Tampa, United States. ⟨inria-00353573⟩



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