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Error-resilient first-order multiplexed source codes: performance bounds, design and decoding algorithms

Hervé Jégou 1 Christine Guillemot 2
1 LEAR - Learning and recognition in vision
GRAVIR - IMAG - Laboratoire d'informatique GRAphique, VIsion et Robotique de Grenoble, Inria Grenoble - Rhône-Alpes, CNRS - Centre National de la Recherche Scientifique : FR71
2 TEMICS - Digital image processing, modeling and communication
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : This paper describes a new family of error-resilient variable-length source codes (VLCs). The codes introduced can be regarded as generalizations of the multiplexed codes described by Je´gou and Guillemot. They allow to exploit first-order source statistics while, at the same time, being resilient to transmission errors. The design principle consists of creating a codebook of fixed-length codewords (FLCs) for high-priority information and in using the inherent codebook redundancy to describe low-priority information. The FLC codebook is partitioned into equivalence classes according to the conditional probabilities of the high-priority source. The error propagation phenomenon, which may result from the memory of the source coder, is controlled by choosing appropriate codebook partitions and index assignment strategies. In particular, a context-dependent index assignment strategy, called crossed-index assignment, is described. For the symbol error rate criterion, the approach turns out to maximize the cardinality of a set of codewords, called the code kernel, offering synchronization properties. The decoder resynchronization capability is shown to be further increased by periodic use of memoryless multiplexed codes. Theoretical and practical performances in terms of compression efficiency and error resilience are analyzed.
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Submitted on : Wednesday, June 10, 2009 - 11:01:34 PM
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Hervé Jégou, Christine Guillemot. Error-resilient first-order multiplexed source codes: performance bounds, design and decoding algorithms. IEEE Transactions on Signal Processing, Institute of Electrical and Electronics Engineers, 2006, pp.1483- 1493. ⟨10.1109/TSP.2006.870609⟩. ⟨inria-00394215⟩



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