A NUMA Aware Scheduler for a Parallel Sparse Direct Solver

Mathieu Faverge 1, 2 Pierre Ramet 1, 2
2 SCALAPPLIX - Algorithms and high performance computing for grand challenge applications
Université Bordeaux Segalen - Bordeaux 2, Université Sciences et Technologies - Bordeaux 1, Inria Bordeaux - Sud-Ouest, École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB), CNRS - Centre National de la Recherche Scientifique : UMR5800
Abstract : Over the past few years, parallel sparse direct solvers have made significant progress. They are now able to solve efficiently real-life three-dimensional problems with several millions of equations. Nevertheless, the need of a large amount of memory is often a bottleneck in these methods. The authors have proposed an hybrid MPI-thread implementation of a direct solver that is well suited for SMP nodes or modern multi-core architectures. Modern multi-processing architectures are commonly based on shared memory systems with a NUMA behavior. These computers are composed of several chip-sets including one or several cores associated to a memory bank. Such an architecture implies hierarchical memory access times from a given core to the different memory banks which do not exist on SMP nodes. Thus, the main data structure of our targeted application have been modified to be more suitable for NUMA architectures. We also introduce a simple way of dynamically schedule an application based on a dependency tree while taking into account NUMA effects. Results obtained with these modifications are illustrated by showing performances of the PaStiX solver on different platforms and matrices.
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Communication dans un congrès
Workshop on Massively Multiprocessor and Multicore Computers, Feb 2009, Rocquencourt, France. 5p., 2008
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Mathieu Faverge, Pierre Ramet. A NUMA Aware Scheduler for a Parallel Sparse Direct Solver. Workshop on Massively Multiprocessor and Multicore Computers, Feb 2009, Rocquencourt, France. 5p., 2008. 〈inria-00416502〉

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