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Schedule-Sensitive Register Pressure Reduction in Innermost Loops, Basic Blocks and Super-Blocks

Abstract : This report makes a massive experimental study of an efficient heuristic for the SIRA framework \cite{sira04}. The heuristic, called SIRALINA \cite{siralina07}, bounds the register requirement of a data dependence graph before instruction scheduling under resource constraints. Our aim is to guarantee the absence of spilling before any instruction scheduling process, without hurting instruction level parallelism if possible. Our register pressure reduction methods are sensitive for both software pipelining (innermost loops) and acyclic scheduling (basic blocks and super-blocks). The SIRALINA method that we experiment in this report is shown efficient in terms of compilation times, in terms of register requirement reduction and in terms of shorted schedule increase. Our experiments are done on thousands standalone DDG extracted from FFMPEG, MEDIABENCH, SPEC2000 and SPEC2006 benchmarks. We consider processor architectures with multiple register type and we model delayed access times to registers. Our register pressure reduction method is distributed as a C independent library (\texttt{SIRAlib}.
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https://hal.inria.fr/inria-00436348
Contributor : Sid Touati <>
Submitted on : Monday, November 30, 2009 - 4:19:36 PM
Last modification on : Friday, January 10, 2020 - 3:42:20 PM
Long-term archiving on: : Tuesday, October 16, 2012 - 2:55:50 PM

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  • HAL Id : inria-00436348, version 1

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CNRS | UVSQ | LARA

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Sébastien Briais, Sid Touati. Schedule-Sensitive Register Pressure Reduction in Innermost Loops, Basic Blocks and Super-Blocks. [Research Report] 2009, pp.53. ⟨inria-00436348⟩

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