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A New Approach of Coding to Improve Speed and Noise Tolerance of On-Chip Busses

Sébastien Pillement 1 Jm. Philippe 2 Olivier Sentieys 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
IRISA-D3 - ARCHITECTURE, Inria Rennes – Bretagne Atlantique
2 LIST - Laboratoire d'Intégration des Systèmes et des Technologies
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Conference papers
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https://hal.inria.fr/inria-00446626
Contributor : Sébastien Pillement <>
Submitted on : Wednesday, January 13, 2010 - 12:25:17 PM
Last modification on : Monday, November 30, 2020 - 7:22:06 PM

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  • HAL Id : inria-00446626, version 1

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CNRS | INRIA | IRISA | UNIV-RENNES1 | IRISA-D3 | INSTITUT-TELECOM | CEA | DRT | UR1-UFR-ISTIC | LIST | UNIV-RENNES | INSA-RENNES

Citation

Sébastien Pillement, Jm. Philippe, Olivier Sentieys. A New Approach of Coding to Improve Speed and Noise Tolerance of On-Chip Busses. International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), Mar 2008, Tozeur, Tunisia. ⟨inria-00446626⟩

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